• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to communication technology. The purpose of the invention is to increase speed. The device contains a matrix of 1 points, 2 switching points, switching points 2 switching points, each of which contains a control circuit 3 and a switching element 4. Element 4 contains a switching transistor, an additional transistor, a sensing transistor, a precharge transistor, and a power source. Depending on the signals from decoders 10 and 11, the corresponding control circuit 3 is activated and element 4 becomes conductive. The coincidence of the row control signal 1 and the column control signal O causes the control circuit 3 to return to the initial state and the corresponding element 4 is locked. 4z.p. f-ly, 5 ill.
    公开号:SU1738105A3
    申请号:SU874203355
    申请日:1987-09-16
    公开日:1992-05-30
    发明作者:Хофманн Рюдигер
    申请人:Сименс Аг (Фирма)；
    IPC主号:
    专利说明:

    The invention relates to communication technology, in particular to switching devices, and can be used in systems for transmitting and exchanging information for broadband communication nodes.
    The purpose of the invention is to increase speed.
    FIG. Figure 1 shows a structural electrical circuit of a device for switching broadband signals; in fig. 24 - structural electrical diagrams of the switching element in PP. 1, 3 and 2 respectively; in fig. 5 - timing charts of the device.
    The switching device of wide-band signals contains a matrix of 1 switching points, switching nodes 2 of switching points, each of which contains a control circuit 3 and a switching element 4.
    The switching element 4 contains a switching transistor 5 and an additional transistor 6.
    The device also contains a reading transistor 7, a pre-charging transistor 8, a power source 9, the first 10 and second 11 control decoders, the first 12 and second 13 input registers.
    The device works as follows.
    Both control decoders 10 and 11 from input registers 12 and 13 can be respectively loaded with a common for row 1 matrix (rows or columns) of switching points with the address of the switching points of the rows or columns they pass to the control line corresponding to the specified address respectively. rows of switching points, control signal 1.
    The coincidence of the horizontal control signal 1 and the column control signal 1 at the intersection point of the corresponding row of matrix 1 with the corresponding column of matrix 1 when establishing the appropriate connection causes activation of the control fixing circuit 3 there, for example, H1. |. The result is that the switching element 4 controlled by this IHIjl control circuit 3, in the example IKIJI element 4, becomes conductive.
    In order to consider the element 4 I Klj I considered in the example, when the corresponding connection is eliminated again to be Locked, the control decoder 10 is again loaded with the corresponding row address coming from the input register 12, so that the line decoder 10 again sends the line control signal 1 to its control line, and at the same time the column decoder 11 is loaded from its input register 13, for example, the idle address or the column address of the non-switched switching nodes 2, so that it delivers a column control over its output line O. The coincidence signal rd row control signal 1 istolbtsovogoup- ravl actuating signal causes return O control circuit 3 | Hij | to its initial state, as a result of which the control element 4lKlji, which is controlled by this control circuit 3, is locked.
    During the preparatory phase (Fig. 5, c), the output lines of the matrix 1 (row lines) through the corresponding pre-charge transistor 8 are at least approximately loaded by the operating potential UDD, for which the pre-charge transistors 8, for example, channel transistors p-type, with the help of the clock signal T o (fig. 5, d) become conductive, at the same time the control of the reading transistors 7, which are channel n-type transistors, is performed by the same clock signal T o in the opposite direction AI, i.e. the transistors are locked, so that the loading of the output lines of the matrix 1 (line lines) can occur independently of the control of the corresponding switching transistor 5 of the individual elements 4 IKIjI.
    Under certain conditions, the potential corresponding to the serially connected binary unit of information can be established on the corresponding input lines of the matrix 1 (column lines) or stored (Fig. 5, b).
    In the next main phase (Fig. 5, d) in the example, the clock signal 1 (Fig. 5, d) the precharge transistors 8 (Fig. 2-4) are locked and the readout transistors 7 are simultaneously unlocked. If now in element 4 I Kij I its switching transistor 5 (Fig. 2-4), which in the example is an n-type channel transistor, due to the switching signal applied to the control input (in example 1) (Fig. 5 a) becomes conductive and thus the switching point is in the switching state, it is now depending on the corresponding switched state of the matrix 1 (column line) prevailing on the corresponding input line that is connected to this input line of matrix 1 through the corresponding element 4 IKijmatrix line 1 (line line) is unloaded or on it
    the pre-phase potential UDD is maintained.
    If the corresponding input line of the matrix 1 (column line) is dominated by the signal O (Fig. 5, b, dashed line) and in accordance with this the n-channel transistor 8 of the pre-charge (Fig. 2-4) of the corresponding element AIKIJI is locked, the corresponding output line of the matrix 1 (line line) is not unloaded through this 4IKIJI element, but the potential state UDD is preserved provided that no switching point matrix 1 (line line) matching this output line is in the switching state neither Conversely, if the input line of the matrix 1 (column line) is dominated by the signal G (Fig. 5, b, solid line) and in accordance with this an additional transistor 6 (Fig. 2-4) of the considered element 4 | Klj |, as well as the switching transistor 5 and the corresponding reading transistor 7, are conductive, the output line of the matrix 1 (line line) is unloaded through this element 41 Klj I and leads to the potential Uss.
    Thus, through a switching point unlocked from its control input, the corresponding input signal is sequentially switched respectively inverted.
    权利要求:
    Claims (5)
    [1]
    In the examples above (Figs. 2-4), the pre-charge transistors 8 are p-type channel transistors, and these channel transistors 8 p-types and being n-type channel transistors 7 are controlled by the same signal T, due to the different types of channels. It is also possible to realize the pre-charge transistors 8 using n-type channel transistors so that if the switching transistors 5, the additional transistors b and the reading transistors 7 are n-type channel transistors, only transistors of the same channel type are used, in order then the control electrodes of the transistors 8 of the precharge and of the sense transistors 7 are again loaded according to the tact that is opposite to the control switching field. The reading transistors 7, as in the foregoing examples of implementation (Figs. 2-4), are again directly fed to the switching field of the clock signal T, and to the n-channel transistors 8, on the contrary, are fed to the inverted switching field of the switching signal. Invention Formula
    1. A switching device for broadband signals containing a matrix of switching points, switching points of switching points, each of which contains a control circuit and a switching element containing a switching transistor, the first electrode of which is connected to the corresponding horizontal of the matrix of switching points, and the control electrode , characterized in that, in order to increase speed, an additional transistor is introduced into the switching elements, the first electrode of which is connected to the second electrode the switching transistor, and the control electrode is connected to the vertical of the switching points matrix, and the second electrode is connected to the first pole of the power source through the readout transducer, while the control electrode of the reading transistor is connected to the clock input and the control electrode of the pre-charge transistor, the first the electrode of which is connected to the second pole of the power source, and the second electrode is connected to the horizontal of the matrix of switching points.
    2. The device according to claim 1, that is, with the fact that the second electrodes of the additional transistors of the respective switching elements are connected by an additional horizontal.
    [2]
    3. Device pop. 1, characterized by the fact that the second electrodes of additional transistors of the corresponding switching elements are combined with an additional vertical.
    [3]
    4. The device according to claim 1, characterized in that all transistors are n-type transistors.
    [4]
    5. The device according to claim 1, wherein the pre-charge transistor is a p-type transistor.
    [5]
    L +
    P
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    引用文献:
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    LU86455A1|1985-10-28|1986-11-13|Siemens Ag|BROADBAND SIGNAL COUPLING DEVICE|
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    LU86915A1|1986-10-07|1987-11-11|Siemens Ag|BROADBAND SIGNAL DEVICE|
    US4897641A|1986-12-04|1990-01-30|Pascom Pty. Ltd.|Space switch|
    LU87431A1|1988-06-08|1989-06-14|Siemens Ag|BROADBAND SIGNAL DEVICE|
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    法律状态:
    优先权:
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